View ADL5303-EVALZ_6241480.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

160 db range 100 pa to 10 ma low cost logarithmic converter data sheet adl5303 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2013 analog devices, inc. all rights reserved. technical support www.analog.com features optimized for fiber optic photodiode interfacing 8 full decades of range law conformance: 0.1 db from 1 na to 1 ma single-supply operation: 3.0 v to 5.5 v complete and temperature stable accurate laser trimmed scaling logarithmic slope of 10 mv/db (at the vlog pin) basic logarithmic intercept at 100 pa easy adjustment of slope and intercept output bandwidth of 10 mhz, 15 v/s slew rate miniature 16-lead package (lfcsp) low power: ~4.5 ma quiescent current (enabled) applications high accuracy optical power measurement wide range baseband log compression versatile detector for apc loops simplified block diagram pdb bias vref i pd vpdb vsum inpt vsum gnd gnd v ps2 pwdn v ps1 vref vlog bfin bfng vo ut 0.5v adl5303 ~10k ? 5k ? 5 2 3 4 15 14 acom 7 11 10 16 12 6 8 9 13 10661-001 temperature compensation figure 1. general description the adl5303 is a monolithic logarithmic detector optimized for the measurement of low frequency signal power in fiber optic systems and offers a large dynamic range in a versatile and easily used form. wide measurement range and accuracy are achieved using proprietary design and precise laser trimming. the adl5303 requires only a single positive supply, v ps , of 5 v. when using low supply voltages, the log slope can be altered to fit the available span. low quiescent current and chip disable facilitate use in battery-operated applications. the input current, i pd , flows in the collector of an optimally scaled npn transistor, connected in a feedback path around a low offset jfet amplifier. the current summing input node operates at a constant voltage, independent of current, with a default value of 0.5 v; this may be adjusted over a wide range. an adaptive biasing scheme is provided for reducing photo- diode dark current at very low light input levels. the vpdb pin applies approximately 0.1 v reverse bias across the photodiode for i pd = 100 pa, rising linearly to 2.0 v of reverse bias at i pd = 10 ma to improve response time at higher power levels. the input pin inpt is flanked by the vsum guard pins that track the voltage at the summing node. connecting the exposed pad of the device to the vsum pins provides a continuous guard to minimize leakage into the inpt pin. the default value of the logarithmic slope at the vlog output is set by an internal 5 k resistor. logarithmic slope can be lowered with an external shunt resistor or increased using the buffer and a pair of external feedback resistors. the addition of a capacitor at the vlog pin provides a simple low-pass filter. the intermediate voltage, v log , is buffered in an output stage that can swing to within about 100 mv of ground and the posi- tive supply, v ps , and provides a peak current drive capacity of 20 ma. an on-board 2 v reference is provided to facilitate the repositioning of the intercept. the incremental bandwidth of a translinear logarithmic amplifier inherently diminishes for small input currents. at i pd =1 na, the bandwidth of the adl5303 is approximately 2 khz increasing in proportion to i pd up to a maximum value of 10 mhz.
adl5303 data sheet rev. 0 | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 simplified block diagram ............................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 4 esd caution .................................................................................. 4 pin configuration and function descriptions ............................. 5 typical performance c haracteristics ............................................. 6 theory of operation ...................................................................... 10 basic concepts ............................................................................ 10 optica l measurements ............................................................... 10 decibel scaling ............................................................................ 10 bandwidth and noise considerations ..................................... 10 chip enable ................................................................................. 11 using the adl5303 ........................................................................ 12 slope and intercept adjustments ............................................. 12 low supply slope and intercept adjustment ......................... 15 changin g the voltage at the summing node ............................ 15 using the adaptive bi as ............................................................. 16 applications information .............................................................. 17 rescaling ...................................................................................... 17 inverting the slo pe ..................................................................... 17 evaluation board ........................................................................ 18 shields and guards ..................................................................... 18 outline dimensio ns ....................................................................... 21 ordering guide .......................................................................... 21 revision history 1 /1 3 rev ision 0 : initial version
data sheet adl5303 rev. 0 | page 3 of 24 specifications v p s = 5 v, gnd, acom = 0 v, t a = 25c, unless otherwise noted. tab le 1 . parameter test conditions/comme nts min 1 typ max 1 unit input interface pin 3 , inpt; pin 2 and pin 4 , vsum specified current range flows toward pin 3 100 pa 10 ma input node voltage internally preset; may be altered 0. 46 0.5 0. 54 v temperature drift ? 40c < t a < +85c 0.0 4 mv/c input guard offset voltage v ofs = v in C v sum ? 20 +20 mv photodiode bias 2 established between v pdb and inpt minimum value i pd = 100 pa 70 100 mv transresistance 200 mv/ma logarithmic output pin 8, vlog slope laser trimmed at 25c 195 200 205 mv/dec 0c < t a < 70c 193 207 mv/dec intercept laser trimmed at 25c 60 100 140 pa 0c < t a < 70c 35 175 pa law conformance error 10 na < i pd < 1 ma, peak error 0.05 0.25 db 1 na < i pd < 1 ma, peak error 0.1 0.7 db maximum output voltage 1.6 v minimum output voltage 0.1 v output resistance laser trimmed at 25c 4.95 5 5.05 k? reference output pin 6 , vref voltage wrt ground laser trimmed at 25c 1.98 2 2.02 v ? 40c < t a < +85c 1.92 2.08 v output resistance 2 ? output buffer pin 9, bfin; pin 13, bfng; pin 11, vou t input offset voltage ? 20 +20 mv input bias current flowing out of pin 9 or pin 13 0.4 a incremental input resistance 35 m? output range r l = 1 k? to ground v p s ? 0.1 v output resistance 0.5 ? wideb and noise 3 i pd > 1 a (see the typical performance characteristics section ) 1 v/hz small signal bandwidth 3 i pd > 1 a (see the typical performance characteristics section ) 10 m hz slew rate 0.2 v to 4.8 v output swing 15 v/s power - down input pin 16 , pwdn logic level, h igh state ? 40c < t a < +85c, 2.7 v < v p s < 5.5 v 2 v logic level, low state ? 40c < t a < +85c, 2.7 v < v p s < 5.5 v 1 v power supply pin 10 and pin 12, vps2 and vps 1 ; pin 14 and 1 5 , gnd supply voltage 3.0 5 5.5 v quiescent current 4.5 5. 6 ma in disabled state 60 a 1 minimum and maximum specified limits on parameters are guaranteed but not tested and are six sigma values. 2 this bias is internally arranged to track the input voltage at i npt; it is not specified relative to ground. 3 output noise and incremental bandwidth are functions of input current; see the typical performance characteristics section .
adl5303 data sheet rev. 0 | page 4 of 24 absolute maximum rat ings table 2 . parameter rating v ps 6 v input current to inpt 20 ma thermal data , 2 - layer jedec board , no air flow (exposed pad soldered to pcb) ja 61.6 c/w jc 1.2c/w maximum power dissipation (exposed pad soldered to pcb ) 0.6 w maximum junction temperature 1 25c operating temperature range ? 40c to +85c storage temperature range ? 65c to +150c lead temperature (soldering 60 sec) 300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
data sheet adl5303 rev. 0 | page 5 of 24 pin con figuration and funct ion descriptions pin 1 indic a t or notes 1. pins labeled nc can be allowed to float, but it is better to connect these pins to ground. avoid routing high speed signals through these pins because noise coupling may result. 2. exposed pad. connect the exposed pad to the vsum pins to provide low leakage guard. 1 nc 2 vsum 3 inpt 4 vsum 1 1 vout 12 vps1 10 vps2 9 bfin 5 vpdb 6 vref 7 acom 8 vlog 15 gnd 16 pwdn 14 gnd 13 bfng adl5303 top view (not to scale) 10661-002 figure 2. pin configuration table 3 . pin function descriptions pin o. nemonic description 1 nc pins labeled nc can be allowed to float, but it is better to connect these pins to ground. avoid routing high speed signals through these pins because noise coupling may result. 2 , 4 vsum guard p ins . vsum is u sed to shield the inpt current line. 3 inpt photodiode current input. connect this pin to the photodiode anode (the photo current flows toward inpt). 5 vpdb photodiode biaser output. connect this pin to the photodiode cathode when using adaptive bias control ; otherwise , leave this pin floating . 6 vref voltage reference output of 2 v . 7 acom analog reference ground . 8 vlog output of the logarithmic front - end processor. r out = 5 k? to ground. 9 bfin buffer amplifier noninverting input (high impedance) . 10 vps2 positive supply, v p s (3.0 v to 5.5 v) . 11 vout buffer output; low impedance . 12 vps1 p ositive supply, v p s (3.0 v to 5.5 v) . 13 bfng buffer amplifier inverting input . 14 , 15 gnd power supply ground connection. 16 pwdn power - down control input. device is active when pwdn is taken low . 17 e pad exposed pad . connect the exposed pad to the vsum pins to provide low leakage guard.
adl5303 data sheet rev. 0 | page 6 of 24 typical performance characteristics 0 0.2 0.4 0.6 0.8 1.0 1.2 1.6 100p 1n 10n 100n 1 10 100 v log (v) i pd (a) 1m 10m 1.4 10661-003 ?40c +25c +85c figure 3. v log vs. i pd 10661-004 error (db) 10mv/db scale ?2.0 i pd (a) ?1.5 ?1.0 ?0.5 0.5 1.5 1.0 2.0 0 +85c ?40c +25c 100p 1n 10n 100n 1 10 100 1m 10m figure 4. logarithmic conformance (linearity) for v log 100p 1n 10n 100n 1 10 100 1m 10m 10661-005 error(db) 10mv/db scale ?1.0 i pd (a) ?0.5 0.5 1.0 0 4.5v 5.0v 5.5v figure 5. absolute deviation from nominal specified value of v log for several supply voltages @ 25c 0.500 0.502 0.504 0.506 0.508 0.510 100p 1n 10n 100n 1 10 100 v sum (v) i pd (a) 1m 10m 10661-006 t a = ?40c, +25c, +85c +85c +25c ?40c figure 6. v sum vs. i pd 0.6 0.8 1. 0 1.2 1.6 1.4 0123456 v pdb (v) i pd (ma) 710 1.8 2 . 0 2 . 2 2 . 4 2 . 6 2.8 89 10661-007 +85c +25c ?40c figure 7. v pdb vs. i pd 0.6 0.8 1. 0 1.2 1.6 1.4 100p 1n 10n 100n 1 10 100 v out (v) i pd (a) 1m 10m 1.8 2.0 2.4 2.2 error ((db) (10mv/db)) 1.25 ?1.00 1.00 0.25 0 ?0.25 ?0.50 0.75 0.50 ?0.75 ?40c +25c +85c t a = ?40c, +25c, +85c v p = 3.0v 10661-008 figure 8. logarithmic conformance (linearity) for a 3 v single supply
data sheet adl5303 rev. 0 | page 7 of 24 ?70 ?60 ?50 ?40 ?30 ?20 0 10 100 1k 10k 100k 1m 10m 100m normalized response (db) frequency (hz) ?10 10na 100na 1a 10 a 100 a 1ma 1na a 10 ma 10661-009 figure 9 . small signal ac response, i pd to v log (5% sine modulation of i pd at frequency) 0.01 1 0.1 10 100 1n 10n 100n 1 10 100 ( v rms/ hz) i pd (a) 1m 10m 10khz 100hz 1khz 1mhz 100khz 10661-010 figure 10 . spot noise spectral density at v log vs. i pd 0.01 1 0.1 10 100 100 1k 10k 10 0k ( v rms/ hz) frequency ( hz ) 1m 10m >100 a 10 a 1a 1na 100na 10na 10661-011 figur e 11 . spot noise spectral density at v log vs. frequency 0 1 2 3 4 5 6 7 8 9 10 1n 10n 100n 1 10 100 wideband noise (mv rms) input current (a) 1m 10m 10661-012 figure 12 . total wideband noise voltage at v log vs. i pd ?12 ?9 ?6 ?3 0 3 100 1k 10k 100k 1m 10m 100m normalized response (db) frequency (hz) gain = 1 , 2, 2.5, 5 a v = 5 a v = 1 a v = 2 a v = 2.5 10661-013 figure 13 . small signal response of buffer ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 10 10 100 1k 10k 100k normalized response (db) frequency (hz) f c =1khz 10661-014 figure 14 . small signal response of buffer operating as two - pole filter
adl5303 data sheet rev. 0 | page 8 of 24 ?2. 0 ?1.5 ?1. 0 ?0.5 0 0.5 100p 1n 10n 100n 1 10 100 error (db) ((10mv/db)) input (a) 1m 10m 1.0 1.5 2.0 t a = 25c mean + 3 mean ? 3 10661-015 figure 15 . logarithmic conformance error distribution (3 to either side of mean) ?5 ?4 ?3 ?2 0 1 100p 1n 10n 100n 1 10 100 error ((db) (10mv/db)) input (a) 1m 10m 2 3 5 ?1 4 mean ? 3 @ 70 c mean + 3 @ 70 c t a = 0c, 70c mean 3 @ 0c 10661-016 figure 16 . logarithmic conformance error distribution (3 to either side of mean) ?5 ?4 ?3 ?2 0 1 100p 1n 10n 100n 1 10 100 error ((db) (10mv/db)) input (a) 1m 10m 2 3 5 ?1 4 t a = ?40c, +85c mean + 3 @ ?40c mean ? 3 @ ?40c mean 3 @ +85c 10661-017 figure 17 . logarithmic conformance error distribution (3 to either side of mean) ?30 ?25 ?20 ?15 0 5 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 v ref drift (mv) temperature ( c ) 90 10 ?10 ?5 15 20 mean + 3 mean ? 3 10661-018 figure 18 . vref drift vs. temperature (3 to either side of mean) ?5 ?4 ?3 ?2 1 2 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 slope change from 25 c (mv/dec) temperature ( c ) 90 ?1 0 3 mean + 3 mean ? 3 10661-019 figure 19 . slope drift vs. temperature (3 to either side of mean) ?50 ?40 ?30 ?20 10 20 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 intercept change from 25 c (pa) temperature ( c ) 90 ?10 0 40 30 mean + 3 mean ? 3 10661-020 figure 20 . intercept drift vs. temp erature (3 to either side of mean)
data sheet adl5303 rev. 0 | page 9 of 24 ?6 ?4 ?2 2 4 ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 v os drift (mv) temperature ( c ) 90 0 8 6 mean + 3 mean ? 3 10661-021 figure 21 . output buffer offset vs. temperature (3 to either side of mean) 0 20 40 80 100 196 198 200 202 hits logarithmic slope (mv/dec ) 204 60 180 120 140 160 10661-022 figure 22 . distribution of logarithmic slope 0 20 40 80 100 60 hits logarithmic intercept (pa ) 60 120 140 160 80 100 120 140 10661-023 figure 23 . distribution of logarithmic intercept 0 20 40 80 100 ?20 hits input guard offset (mv ) 60 180 120 140 160 ?10 0 10 20 10661-024 figure 24 . distribution of input guard offset voltage v ofs (v inpt C v sum )
adl5303 data sheet rev. 0 | page 10 of 24 theory of operation basic concepts the adl5303 uses an advanced circuit implementation that exploits the logarithmic relationship between the base - to - emitter voltage, v be , and collector current, i c , in a bipol ar transistor. using these principles , the relationship between the input current , i pd , applied to the inpt pin , and the voltage appearing at the inter mediate output vlog p in is: v log = v y log 10 ( i pd / i z ) ( 1 ) w here: v y is the voltage slope (in the case of b ase - 10 logarithms, it is also referred to as volts per decade). i z is t he fixed current in the logarithmic equation called the intercept. in the following example , t he scaling is chosen so that v y is trimmed to 200 mv/ decade (10 mv/db). the intercept is p ositioned at 100 pa; the output voltage , v log , cross es zero when i pd is of this value. however , the actual v log must always be slightly above ground. using equation 2, calculate the output for any value of i pd . thus, for an input current of 25 na , v log = 0 .2 v log 10 (25 na /100 pa ) = 0.4796 v ( 2 ) in practice, both the slope and intercept can be altered, to either higher or lower values, without any significant loss of calibration accuracy, by using one or two exter nal resistors, often in conjunc tion with the trimmed 2 v voltage reference at the vref p in . optical measurements when interpreting the i pd current in terms of optical power inci dent on a photodetector, it is necessary to be clear about the conversion (optical power to current) properties of a reverse biased photodiode. the units of this conversion are expres sed in amps per watt and referred to as photodiode responsivity , . for the typical ingaas pin photodiode , the responsivity is a pproximately 0.9 a/w. it is important to note that i n purely electrical circuits , current and power are not related in this proportional manner. a c urrent applied to a resistive load results i n a power propor - tional to the square of the current , p = i 2 r. the difference in scaling for a photodiode is because i pd flow in a reverse - biased diode is larg e ly dependent on the fixed built - in voltage of the pn junction and is relatively insensitive to t he external bias voltage . in the detector diode , power dissipated is proportional to the i pd current and the relationship of i pd to the optical power, p opt , is preserved. i pd = p opt ( 3 ) the same relationship exists between the intercept current, i z , and an equivalent intercept power, p z , thus, i pz = p z ( 4 ) therefore , equation 1 can be written as v log = v y log 10 ( p opt / p z ) ( 5 ) for the adl5303 operating in its default configuration , an i z of 100 pa corresponds to a p z of 110 pw , for a diode having a responsivity of 0.9 a/w. t hus, an optical power of 3 mw generate s v log = 0.2 v log 10 (3 mw /110 pw ) = 1 487 v ( 6 ) note that when using the adl5303 in optical applications the v log output is referred t o in terms of the equivalent optical power, the logarithmic slope remains 10 mv/d b at this output. this can be confusing because a decibel change on the optical side has a different mean ing than on the electrical side. in either case, the logarithmic slope can always be expressed in units of m illivolts per decade to help eliminate confusion. decibel scaling when power levels are expressed as decibels above a reference level (in dbm, for a reference of 1 mw), the logarithmic conver - sion has a lready been perfor med, and the log ratio in the previous expressions becomes a simple difference. be careful in assignin g variable names here, because p is often used to denote actual power as well as this s ame power expressed in decibels; how - ever, these are numerically different quantities. bandwidth and noise considerations r esponse time and wideband noise of translinear log amps are a function of the signal current , i pd . b andwidth becomes progres sively lower as i pd is reduced, largely due to the effects of junction capacitances in the translinear device . figure 9 shows ac response curve s for the adl5303 at eight repre sentative currents of 1 n a to 10 ma, using r 1 = 750 ? and c1 = 1000 pf. the values for r1 and c1 ensure stability over the full 160 db dynamic range . more optimal values may be used for smaller subranges. a certain amount of experi - mental trial and error may be necessary to select the optimum input network component values for a given application. the relationship between i pd and the voltage noise spectral density, s nsd , associated with the v be of q1, calculates to the following: pd nsd i s 7 . 14 = ( 7 ) w here : s nsd is nv/hz. i pd is expressed in microa mps. t a = 25c.
data sheet adl5303 rev. 0 | page 11 of 24 for an input of 1 na, s nsd evaluates to almost 0.5 v/ hz; assum ing a 20 khz bandwidth at this current, the integrated noise voltage is 70 v rms. however, th is calculation is not complete. the basic scaling of the v be is approximately 3 mv/db; translated to 10 mv/db, the noise predicted by equation 7 must be multi plied by approximately 3.33. the additive noise effects associated with the reference transistor, q2, and the temperature compen sation circuitry must also be included. the final voltage noise spectral density presented at the vlog p in varies inver sely with i pd , but is not a simple square root relationship. figure 10 shows the measured noise spectral density vs . frequency at the vlog output, for the same nine - decade spaced values of i pd . chip enable power down t he adl5303 by taking the pwdn p in to a high logic level. the residual supply current in the disabled mode is ty pically 60 a.
adl5303 data sheet rev. 0 | page 12 of 24 using the adl5303 the default configuration ( see figure 2 5 ) include s a 2.5:1 atten - uator in the feedback path around the buffer. this increases the slope of 10 mv/db at the vlog p in to 25 mv/db at vout . for the full dynamic range of 160 db (80 db optical), the output swing is 4.0 v, which can be accommodated b y the rail - to - rail output stage when using the recommended 5 v supply. the capacitor from vlog to ground forms an optional single - pole low - pass filter. because the resistance at this pin is trimmed to 5 k, an accurate time c onstant can be realized. for ex ample, with c flt = 10 nf, the ? 3 db corner frequency is 3.2 khz. such filtering is useful in minimizing the output noise, particularly when i pd is small. m ultipole filters are even more ef fec tive in reducing noise. a capacitor between vsum and ground is essential for minimizing the noise on this node. when the bias voltage at either vpdb or vref is not needed , these pins should be left unconnected. slope and intercept adjustments the choi ce of slope and intercept depends on the application. the versatility of the adl5303 permits optimal choices to be made in two common situations. first, it allows an input current range of less than the full 160 db to use the available voltage span at the output. second, it allows this output voltage range to be optimally positioned to fit the input capa city of a subsequent adc. in special applications, very high slopes, such as 1 v/dec ade , allow small subranges of i pd to be covered at high sensitivity. the slope can be lowered without limit by the addition of a shunt resistor, r s , from vlog to ground. b ecause the resistance at this pin is trimmed to 5 k, the accuracy of the modified slope depend s on the external resistor. it is calculated by, k 5 + = s s y y r r v v ( 8 ) for example, using r s = 3 k ? , the slope is lowered to 75 mv per decade or 3.75 mv/db. table 4 provides a selection of suitable values for r s and the resulting slopes. table 4 . examples of lowering the slope r s (k?) v y (mv/dec ade ) 3 75 5 100 15 150 in addition to uses in filter a nd comparator functions, the buffer amplifier provides the means to adjust both the slope and inter cept, which require a minimal number of external components. the high input impedance at bfin, low input offset voltage, large output swing, and wide bandwi dth of this amplifier permit numerous transformations of th e basic v log signal, using stan dard op amp circuit practices. for example, it has been noted that to raise the gain of the buffer, and therefore the slope, a feedback attenuator, r a and r b in figure 25 , should be inserted between vlog and the inverting input bfng p in . nc v out 500mv/dec 200mv/dec r18 (r b ) 10k ? ~10k ? r15 (r a ) n? 5k ? c7 (c filt ) nc nc = no connect v p 100nf r1 750 c1 1nf i pd c3 pdb bias vref vpdb vsum inpt vsum acom vps2 pwdn vps1 vref vlog bfin bfng vout 0.5v adl5303 5 2 3 4 15 14 gnd gnd 7 1 1 10 16 12 6 8 9 13 temper a ture compens a tion 10661-025 figure 25 . basic connections (r 15 , r 18, c 7 are optional; r1 and c1 are the default values )
data sheet adl5303 rev. 0 | page 13 of 24 a wide range of gains may be used and the resistor magnitudes are not critical; their parallel sum should be about equal to the net source resistance at the noninverting input. when high gains are used, the output dynamic range is reduced; for a maxi mum swing of 4.8 v, it amount s to 4.8 v/v y decades. thus, using a ratio of 3 , to set up a slope 30 mv/db (600 mv/ decade), ei ght decades can be handled, wh e reas with a ratio of 5 , which sets up a slope of 50 m v/db (1 v/decade), the dynamic range is 4.8 decades, or 96 db. when using a lowe r supply voltage, the calculation proceeds in the same way, remembering to first subtract 0.2 v to allow for 0.1 v upper and lower headroom in the output swing. alteration of the logarithmic intercept is only slightly more tricky. first , note that it is rarely necessary to lower the intercept below a value of 100 pa, because thi s merely raises all output volt ages further above ground. howeve r, where this is required, the first step is to raise the voltage , v log , by connecting a resistor, r z , from vlog to vref (2 v) as shown in figure 26. this has the effect of elevating , v log , for small inputs while lower ing the slope to some extent because of the shunt effect of r z on the 5 k? output resistance. i f necessary, the slope may be increased as before, using a feedback attenuator around the buffer. table 5 lists some examples of lowering the intercept combined with several slope variations. table 5 . examples of lowering the intercept v y (mv/decade) i z (pa) r a (k?) r b (k?) r z (k?) 200 1 20.0 100 25 200 10 10.0 100 50 200 50 3.01 100 165 300 1 10.0 12.4 25 300 10 8.06 12.4 50 300 50 6.65 12.4 165 400 1 11.5 8.2 25 400 10 9.76 8.2 50 400 50 8.66 8.2 165 500 1 16.5 8.2 25 500 10 14.3 8.2 50 500 50 13.0 8.2 165 use the following e quation with table 5 : ? ? ? ? ? ? ? ? + + ? ? ? ? ? ? ? ? + = 10 log ( 9 ) w here g = 1 + r a /r b and r log = 5 k . nc v out 500mv/dec r18 (r b ) r14 (r z ) r15 (r a ) nc = no connect v p 100nf r1 750 ? c1 1nf i pd c3 pdb bias vref vpdb vsum inpt vsum acom vps2 pwdn vps1 vref vlog bfin bfng vout 0.5v adl5303 ~10k ? 5k ? 5 2 3 4 15 14 gnd gnd 7 11 10 16 12 6 8 9 13 temperature compensation 10661-026 figure 26 . method for lowering the intercept
adl5303 data sheet rev. 0 | page 14 of 24 generally, it is useful to raise the intercept. keep in mind that this moves the v log line in figure 26 to the right, lowering all ou tput values. figure 27 shows how raising the intercept is achieved. the feedback resistors, r a and r b , around the buffer are now augmented with a third resistor, r z , placed between the bfng and vref p ins . adding a third resistor r aises the zero - signal voltage on bfng, which has the effect of pushing v out lower . note that the addition of the r z resistor also alters the feedback ratio. however, this change in feedback ratio is readily compensated in the design of the network. table 6 lists the resistor values for representative intercepts. table 6 . examples of raising the intercept v y (mv/decade) i z (na) r a (k?) r b (k?) r c (k?) 300 10 7.5 37.4 24.9 300 100 8.25 130 18 .2 400 10 10 16.5 25.5 400 100 9.76 25.5 16.2 400 500 9.76 36.5 13.3 500 10 12.4 12.4 24.9 500 100 12.4 16.5 16.5 500 500 11.5 20.0 12.4 use the following equation with table 6 : ? ? ? ? ? ? ? ? + = ? ? ? ? ? ? ? ? = 10 log (1 0 ) w here . and 1 b a b a b a c b a r r r r r r r r r g = + = nc v out 500mv/dec r15 (r a ) r18 (r b ) nc = no connect v p 100nf r1 750 c1 1nf i pd c3 pdb bias vref vpdb vsum inpt vsum acom vps2 pwdn vps1 vref vlog bfin bfng vout 0.5v adl5303 ~10k ? 5k ? 5 2 3 4 15 14 gnd gnd 7 11 10 16 12 6 8 9 13 temperature compensation r13 (r c ) 10661-027 figure 27 . method for raising the intercept
data sheet adl5303 rev. 0 | page 15 of 24 low supply slope and intercept adjustment when using the device with a supply of less than 4 v, it is necessary to reduce the slope a nd intercept at the vlog pin to preserve good log conformance over the entire 160 db oper - ating range. the voltage at the vlog pin is generated by an internal current source with an output current of 40 a/decade feeding the internal laser trim med output resistance of 5 k. when the voltage at the vlog pin exceeds v p ? 2.3 v, the current source ceases to respond linearly to logarithmic increases in current. avoid headroom issue s by reducing the logarithmic slope and intercept at the vlog pin an d by connecting an external resistor , r s , from the vlog pin to ground in combination with an intercept lowering resistor , r z . the values shown in figure 28 illustrate a good solution for a 3.0 v positive supply. th e resulting logarithmic slope measured at vlog is 62.5 mv/decade with a new intercept of 57 fa. the original logarithmic slope of 200 mv/decade can be recovered using voltage gain on the internal buffer amplifier. changin g the voltage at the summing node the default value of vsum is determined by using a quarter of vref (2 v). this can be altered by applying an independent voltage source to vsum, or by adding an external resistive divider from vref to vsum. this network operate s in parallel with the inter nal divider (40 k? and 13.3 k), and the choice of external resistors should take this into account. in practice, the total resistance of the added string may be as low as 10 k? (consuming 400 a from vref). low values of vsum and thus v ce are not advised when large values of i pd are expected. nc v out 500mv/dec r18 (r b ) c7 (r s ) 2.67k ? r14 (r z ) 15.4k? r15 (r a ) 4.98k ? 2.26k ? nc = no connect v p 100nf r1 750 ? c1 1nf i pd c3 pdb bias vref vpdb vsum inpt vsum acom vps2 pwdn vps1 vref vlog bfin bfng vout 0.5v adl5303 ~10k ? 5k? 5 2 3 4 15 14 gnd gnd 7 11 10 16 12 6 8 9 13 temperature compensation 10661-028 figure 28 . recommended low supply application circuit
adl5303 data sheet rev. 0 | page 16 of 24 using the adaptive b ias for most photodiode applications, the placement of the anode somewhat above ground is acceptable, as long as the positive bias on the cathode is adequate to support the peak current for a particular diode, limited mainly by its series resistance. to address this matter, the adl5303 provides for a diode b ias that increases linearly with the current. this bias voltage appears at the vpdb p in , and varies from 0.6 v (reverse - biasing the diode by 0.1 v) for i pd = 100 pa and rises to 2.6 v (for a diode bias of 2 v) at i pd = 10 ma. this results in a constant internal junction bias of 0.1 v when the series resistance of the photodiode is 200 . for optical power measurements over a wide dynamic range , the adaptive biasing function is valuable in minimizing dark current while preventing the loss of photodiode bias at high currents. use of the adaptive bias feature is shown in figure 29. capacitor cpb, between the photodiode cathode at the vpdb p in and ground, is included to lower the impedance at this node and thereby improve the high frequency accuracy at current levels where the adl5303 bandwidth is high. cpb also ensures a high frequency path for any high frequency modulation on the optical signal, which might not otherwise be accurately averaged. cpb is not necessary in all cases, and experimentation may be required to find an optimum value. nc v out 500mv/dec r18 (r b ) c7 (c filt ) r15 (r a ) 15k ? 10k ? nc = no connect v p 100nf r1 750 c1 1nf cpb r25 i pd c3 pdb bias vref vpdb location vsum inpt vsum acom vps2 pwdn vps1 vref vlog bfin bfng vout 0.5v adl5303 ~10k ? 5k ? 5 2 3 4 15 14 gnd gnd 7 11 10 16 12 6 8 9 13 temperature compensation 10661-029 figure 29 . using the adaptive biasing
data sheet adl5303 rev. 0 | page 17 of 24 applications information smaller input voltages can be measured accurately when aided by a small offset nulling voltage applied to vsum. the minimum voltage that can be accurately measured is limited only by the drift in the input offset of the adl5303 . the specifications show the maximum spread over the full temperature and supply range. over a limited temperature range and with a regulated supply, the o ffset drift is lower; in this situation, processing of inpu ts down to 5 mv is practicable. rescaling the use of a much larger value for the intercept may be useful in certain situations. in this example, it has been moved up four decades, from the default value of 100 pa to the center of the full eight - decade range at 1 ma. using a voltage input as previ - ously described, this corresponds to an altered voltage mode intercept, v z , which is 1 v for r in = 1 m. to take full advantage of the larger output swing , the gain of the buffer has been increased to 4.53 , resulting in a scaling of 900 mv/decade z and a full - scale output of 3.6 v. inverting the slope the buffer is essentially an uncommitted op amp that can be used to support the operation of the adl5303 in a variety of ways. it can be completely disconnected from the signal chain when not needed. figure 30 shows its use as an inverting ampli - fier; this changes the polarity of the slope. the output can be repositioned to a positive value by applying a fraction of v ref to the bfin p in . the full design for a practical application is left undefined in this brief illustration, but a few cases are discussed , as follows . for example, if slope of ? 30 mv/db is needed ; a gain of 3 is required . because v log exhibits a source resistance of 5 k, r a must be 15 k. a positive offset, v os , is applied to the bfin pin, as indicated in figure 30. the resulting outp ut voltag e can be expressed as os z pd y a out v i i v r v + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = 10 log k 5 (1 1 ) when the gain is set to 13 ( r a = 5 k) , the 2 v v ref can be tied directly to bfin, in which case the starting point for the output response is at 4 v. however, because the slope in this case is only ? 0.2 v/decade, t he full current range take s the output down by only 1.6 v. clearly, a high er slope (or gain) is desirable; in which case , set v os to a smaller voltage to avoid railing the output at low currents. if v os = 1.2 v and g = 33, vout now starts at 4.8 v a nd fall s through this same voltage toward ground with a slope of ? 0.6 v per decade, spanning the full range of i pd . nc v out r15 (r a ) v os nc nc = no connect v p 100nf r1 750 ? c1 1nf i pd c3 pdb bias vref vpdb vsum inpt vsum acom vps2 pwdn vps1 vref vlog bfin bfng vout 0.5v adl5303 ~10k ? 5k ? 5 2 3 4 15 14 gnd gnd 7 11 10 16 12 6 8 9 13 temperature compensation 10661-030 figure 30 . using the buffer to invert the polarity of the slope
adl5303 data sheet rev. 0 | page 18 of 24 evaluation board an evaluation board is available for the adl5303 , the sche - matic for which is shown in figure 31 , and the board layout is shown in figure 32 and figure 33 . it can be configured for a wide variety of experiments. the board is factory set for p hotoconductive m ode with a buffer gain of unity, providing a slope of 10 mv/db and an intercept of 100 pa. by substituting resi stor and capacitor values, all of the application circuits presented in this data sheet can be evaluated . the system is completed by the fi nal buffer amplifier, which is an uncommitted op amp with a rail - to - rail output capability, a 10 mhz bandwidth, and good load driving capabilities. the buffer can be used to implement multipole low - pass filters for noise reduction. the buffer also facilitates modification of the output scaling and the intercept point using simple resistor divider networks and the 2 v ou tput provided by the vref pin. shields and guards reducing errors from external sources in a current sensing circuit requires a different approach then the voltage sensing input of the typical high impedance op - amp circuit. leakage can be a significant sou rce of error for highly sensitive log amps, especially at the low end of their range. for example, a 1 g leakage path to ground from the i npt input with a v sum set to the default 0 .5 v generate s a 0 .5 na offset. the adl5303 evaluation board makes extensive use of guards to reduce the effects of leakage at low input levels . i t is important to carefully handle and clean the adl5303 eval uation board to prevent contaminants from handling or improper washing of the pcb causing leakage currents. circuit board designs for the adl5303 must connect the epa d to the vsum pins to provide a contin uous guard around the sensitive inpt pin to reduc e the influence of surface contaminants . a common mistake for those unfamiliar with low level current sensing is to attach a high impedance scope probe or meter to measure the input for debug. this can cause significant error, as the typical 1m ~ 100 m impedance of these probes source s / sink s current from the input , depending on their bias. in instrumentation applications where measurements <1 na are required, the use of triaxial cables and connectors is common to reduce leakage through the insulating dielectric by carrying a continuous guard from current source to sensing circuit on the intermediate conductor. this type of guarding circuit is differ - ent from a conventional electrostatic shield used in voltage sensing applications. an electrostatic shie ld relies on low impedance and the ability to flow current freely to minimize voltage induced on the shield that can capacitively couple into a high impedance input. a guard is actively driven to the same voltage as the current carrying center conductor e liminating leakage through the dielectric between the center conductor and the guard. the guard does not flow current other th a n the leakage from the guard to the outer shield . the guard is usually connected to a single end of the cable only because any si gnifi - cant current flow through the guard can couple inductively to the center conductor. using the adl 5303 evaluation board , the guard can be driven either from the guard of an external current source or from the internal vsum bias of the adl5303 . the adl5303 evaluation board can bias the shield of a coaxial cable connected to the inpt input to the nominal v sum voltage with switch s1 but this requires careful consideration of the environment on the other side of the cable. for example if the adl5303 evaluation board is configured for v sum = 0 .5 v connecting the other end of the inpt coaxial cable to an instrument with a ground referenced shield pull s v sum to ground and collapse s the input stage of the adl5303 . floating the current source end of the shield provide s a low leakage guard but a separate return path for the signal current must then be prov ided . if cable dielectric leakage is not a concern , the inpt can be connected directly to a coaxial cable with the shield providing a signal ground .
data sheet adl5303 rev. 0 | page 19 of 24 acom pwdn 14 vpos 0? dni vps1 0? 0? 0? dni 0? 10k? 1000pf 0 ? 0? 0? 1000pf vsum 0.1f vsum vps2 bfin vref vlog vout vpdb 750 ? inpt bfng vpos gnd2 r10 10k? r1 c2 c7 (c filt or r s ) 0.1 f s1 1 3 2 s2 1 3 2 r3 r5 dni r6 dni r7 dni c3 0.1 f c1 u1 1 10 1 1 12 13 15 16 2 3 4 5 6 7 8 9 p ad inpt vpdb r2 0? r8 dni r9 dni r13 (r c ) r14 (r z ) r17 r22 r20 0? vlog_out vpos c6 acom r12 0? r15 (r a ) 15k ? buffer_out r16 c5 0.1f c8 0.1f r21 r18 (r b ) r19 dni gnd1 vref gnd2 r4 r23 r24 r25 or (cpb) dni r26 r11 dni agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd agnd nc gnd gnd dni = not installed in default configuration 10661-031 0? figure 31 . schematic
adl5303 data sheet rev. 0 | page 20 of 24 10661-032 figure 32 . component side layout 10661-033 figure 33 . component side silkscreen table 7 . evaluation board configuration options compon ent function default condition vp os , agnd positive supply and ground pins . s1 device enable . when s1 is in the 0 position, the pwdn p in is connected to ground and the adl5303 is in its normal operating mode. s1 = installed s2 guard/shield options . the shells of the sma connectors used for the input and the photodiode bias can be set to the voltage on the vsum p in or connected to ground. when s2 is in the 0 position , the sma shell is connected to vsum. s2 = installed r13 (r c ) , r 1 4 (r z ) intercept adjustment . a dc offset can be applied to the input terminals of the buffer amplifier to adjust the effectiv e logarithmic intercept. r 1 3 = open (size 0603) r 1 4 = open (size 0603) r5, r6, r7, r8, r9 bias adjustment . the voltage on the vsum and inpt pins can be altered using appropriate resistor values. r5 , r6 , r7 = open (size 0603) r8, r 9 = open (size 0603) r 15 (r a ), r18 (r b ) slope adjustment. r15 = 15 k ? (size 0603) r18 = 10 k ? (size 0603) c3 vsum decoupling capacitor. c3 = 0.1 f (size 0603) c6 supply decoupling capacitor . c6 = 0.1 f (size 0603) r25 ( c pb ) photodiode biaser decoupling . provides high frequency decoupling . r25 = open (size 0603) c5, c7 ( c filt or r s ) , c8, r11, r1 6 , r1 7 , r1 9, r20 output filtering . allows implementation of a variety of filter configurations, from simple rc low - pass filters to three - pole sallen and key filters . r11, r19 , c5 = open (size 0603) r1 6, r17, r 20 = 0 ? (size 060 3) c 7, c 8 = 0.1 f (size 0603) r1 , c1 input filtering . provides essential hf compensation at the input p in , inpt. r1 = 750 ? (size 0 402 ) c 1 = 1 nf (size 0603) r2, r3, r4, r23, r24, r21, r22, r12, r26 isolation jumpers. all = 0 ? (size 0603)
data sheet adl5303 rev. 0 | page 21 of 24 outline dimensions 3.10 3.00 sq 2.90 0.30 0.25 0.20 1.65 1.50 sq 1.45 1 0.50 bsc bottom view top view 16 5 8 9 12 13 4 exposed pad p i n 1 i n d i c a t o r 0.50 0.40 0.30 seating plane 0.05 max 0.02 nom 0.20 ref 0.20 min coplanarity 0.08 pin 1 indicator 0.80 0.75 0.70 compliant to jedec standards mo-220-weed-6. for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 01-26-2012-a figure 34. 16-lead lead frame chip scale package [lfcsp_wq] 3 mm 3 mm body, very very thin quad (cp-16-27) dimensions shown in millimeters ordering guide model 1 temperature range package description package option branding ordering quantity adl5303acpz-r2 ?40c to +85c 16-lead lfcsp_wq cp-16-27 h38 250 adl5303acpz-r7 ?40c to +85c 16-lead lfcsp_wq, 7 tape and reel cp-16-27 h38 1500 adl5303acpz-rl ?40c to +85c 16-lead lfcsp_wq, 13 tape and reel cp-16-27 h38 5000 ADL5303-EVALZ evaluation board 1 z = rohs compliant part.
adl5303 data sheet rev. 0 | page 22 of 24 notes
data sheet adl5303 rev. 0 | page 23 of 24 notes
adl5303 data sheet rev. 0 | page 24 of 24 notes ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10661 - 0 - 1/13(0)

▲Up To Search▲

Price & Availability of ADL5303-EVALZ

	To Download ADL5303-EVALZ Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .